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Fundamentals of FPGA Design
Course Objectives:
Use the ISE software tools to implement a design and gain a
firm understanding of the Xilinx FPGA architecture. Learn the best
design practices from the pros and understand the subtleties of the
Xilinx design flow. This course covers ISE 8.2i features, such as
the Architecture Wizard, the Pin and Area Constraint Editor (PACE)
and iMPACT. Other topics include design planning, implementation
options, and global timing constraints.
Who should attend?
This course is specially designed for R&D engineers working in
high tech electronics or defiance industry.
Prerequisites:
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Working HDL knowledge (VHDL or Verilog)
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Digital design experience
Skills Gained:
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Use Xilinx Project Navigator to implement an FPGA design
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Assign pin locations with the PACE tool
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Create DCM instantiations with the Architecture Wizard
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Read reports to determine whether design goals were met
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Use the Constraints Editor to enter basic global timing
constraints
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Locate and modify implementation optionsf
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Real-time FPGA configuration with iMPACT tool
Software
Tools:
Lab
Descriptions:
The labs for this course provide a practical foundation for creating
synthesizable RTL code. All aspects of the design flow are covered
in the labs. The labs are written, synthesized, behaviorally
simulated, and implemented by the student. The focus of the labs is
to write code that will optimally infer reliable and
high-performance circuits. The labs culminate in a functional
calculator that students verify in simulation.
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Lab 1: Xilinx Tool Flow Create a new project in the ISE
Project Navigator and use the Architecture Wizard and PACE tool
in the design process. Implement a design by using default
software options. The design will be simulated.
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Lab 2: Architecture Wizard and PACE Use the Architecture
Wizard to customize a DCM and incorporate the DCM into the
design. Use PACE to assign pin locations and implement the
design.
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Lab 3: Global Timing Constraints Enter global timing
constraints with the Xilinx Constraints Editor. Review the
Post-Map Static Timing Report to verify that the timing
constraints are realistic. Use the Post-Place & Route Static
Timing Report to determine the delay of the longest constrained
path for each timing constraint.
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Lab 4: Implementation Options Adjust process properties and
I/O configuration options to improve the design performance.
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Lab 5: FPGA Configuration Create configuration BIT and PROM
file. Configure FPGA using Serial slave and JTAG mode using
iMPACT tool.
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